1. Field of the Invention
The invention relates to a memory device, such as an SRAM, that has different read and write clock signals.
2. Description of the Related Art
Referring to FIG. 1, a conventional memory device is shown to comprise a global decoder circuit 11, two pairs of memory cell arrays 12 each of which is disposed adjacent to a respective one of opposing first and second sides of the global decoder circuit 11 and is coupled to the global decoder circuit 11, a write control circuit 13 coupled to and disposed adjacent to a third side of the global decoder circuit 11 between the first and second sides, a read control circuit 14 coupled to and disposed adjacent to a fourth side of the global decoder circuit 11 opposite to the third side, a pre-decoder circuit 15 coupled to the global decoder circuit 11 and the read control circuit 14 and disposed between the fourth side of the global decoder circuit 11 and the read control circuit 14, a read clock buffer 16 disposed on one side of the read control circuit 14 opposite to the pre-decoder circuit 15, a write clock buffer 17 disposed on one side of the read clock buffer 16 opposite to the read control circuit 14, and a pair of data input buffers 18, each of which is disposed at the third side of the global decoder circuit 11 adjacent to a respective one of the pairs of memory cell arrays 12, and is coupled to an external data input device (not shown), the respective one of the pairs of memory cell arrays 12 and the write clock buffer 17. The global decoder circuit 11 includes a write global decoder portion 111 and a read global decoder portion 112. Each memory cell array 12 includes a local decoder portion 121 between two mxn cell array portions 122. A multiplexer (MUX) 123 has an input side coupled to bit lines of the cell array portions 122 of the memory cell arrays 12. A sense amplifier (SA) 124 is coupled to an output side of the multiplexer 123. An output circuit (DO) 125 is coupled to an output end of the sense amplifier 124, and is further coupled to the read clock buffer 16.
A write operation for the aforesaid conventional memory device is conducted as follows: Input data to the memory cell arrays 12 are initially sent to the data input buffers 18. When write address sets corresponding to the input data are received by the write control circuit 13, the latter generates appropriate write address and write control signals that are provided to the write global decoder portion 111 of the global decoder circuit 11 to enable writing of the input data into the memory cell arrays 12. At this time, the write global decoder portion 111 and the local decoder portions 121 of the memory cell arrays 12 decode the write address sets so that appropriate ones of the memory cells of the cell array portions 122 are activated. Write clock signals from the write clock buffer 17 are received by the data input buffers 18 so as to control the transmission of the input data from the data input buffers 18 to the memory cell arrays 12. The input data are written into the activated ones of the memory cells of the cell array portions 122 at this stage.
A read operation for the aforesaid conventional memory device is conducted as follows: When read address sets are received by the read control circuit 14, the latter generates appropriate read address and read control signals to the global decoder circuit 11 to enable reading of the memory cell arrays 12. At this time, the pre-decoder circuit 15, the read global decoder portion 112 and the local decoder portions 121 of the memory cell arrays 12 decode the read address sets so that appropriate ones of the memory cells of the cell array portions 122 are activated. Data in the activated ones of the memory cells of the cell array portions 122 are received by the multiplexer 123. The output of the multiplexer 123 is sensed by the sense amplifier 124, and is provided to the output circuit 125. Read clock signals from the read clock buffer 16 are received by the output circuit 125 to control the transmission of output data to an external device (not shown).
Some of the drawbacks of the aforesaid conventional memory device are as follows:
1. Because the write clock buffer 17 and the data input buffers 18 are disposed on opposite sides of the global decoder circuit 11, the distance between the write clock buffer 17 and the data input buffers 18 is relatively long such that parasitic effect is not negligible and can affect adversely synchronized transmission of the input data to the memory cell arrays 12.
2. The signal strength at the bit lines of the cell array portions 122 is relatively weak, and is further weakened by coupling between the bit lines and the multiplexer 123, thereby leading to errors in the data sensed by the sense amplifier 124.
3. The memory cell arrays 12 are relatively large due to the presence of the local decoder portions 121. The large memory cell arrays 12 require relatively long global word lines for connection to the global decoder circuit 11. The relatively long global word lines are prone to errors due to parasitic effect.